A Novel Approach to FPGA-Based Hardware Fault Modeling and Simulation

The purpose of this work is to present a Hardware Fault Simulation (HFS) methodology and tool (fs), using partial reconfiguration, suitable for efficient fault modeling and simulation in FPGAs. The methodology is particularly useful for BIST effectiveness evaluation, and for applications in which multiple fault injection is mandatory, such as in safety-critical applications. A novel (CSA – Combination Stuck-At) fault model is proposed, which leads to better test quality estimates than the classic (LSA – Line StuckAt) model at the LUTs terminals. Fault injection is performed using only local reconfiguration with small binary files. The efficiency of Software and FPGAbased HFS, with and without partial reconfiguration, are compared using ISCAS’89 sequential benchmarks, showing the usefulness of the proposed methodology.